A multi-processor chip includes several processors that communicate with one another, and may share certain addresses in a memory for storing data that are commonly used by the processors. The memory may reside in a chip separate from the multi-processor chip. One processor may have an on-chip cache memory to facilitate faster access of often used data. The cache memory may be accessible to only one processor and not accessible to other processors. Because the cache memory is not shared among different processors, certain procedures are followed in order to maintain memory coherency, i.e., ensure that all of the processors are accessing the same data when reading from or writing to the same shared address.
One method of enforcing memory coherency is to mark the memory locations that are shared between the processors as uncachable. The processors access the external main memory each time data is retrieved from or written to these shared addresses without accessing the cache memory. Another method of enforcing memory coherency is to invalidate the shared address locations prior to reading from them and flushing the shared address locations after writing to them. This may involve calling flush subroutines or invalidate subroutines, storing data in a stack, calculating cache line boundaries, flushing or invalidating a cache line, retrieving the data from the stack, and returning from the subroutine.